Hitachi SH7750 series Hardware Manual page 321

Table 13.6 (1) 64-Bit External Device/Big-Endian Access and Data Alignment
Operation
Access
Size Address No. D63–56
Byte 8n 1
8n+1 1
8n+2 1
8n+3 1
8n+4 1
8n+5 1
8n+6 1
8n+7 1
Word 8n 1
8n+2 1
8n+4 1
8n+6 1
Long- 8n 1
word
8n+4 1
Quad- 8n 1
word
Rev. 4.0, 04/00, page 310 of 850
D55–48 D47–40
Data — —
7–0
— Data —
7–0
— — Data
7–0
— — —
— — —
— — —
— — —
— — —
Data Data —
15–8 7–0
— — Data
15–8
— — —
— — —
Data Data Data
31–24 23–16 15–8
— — —
Data Data Data
63–56 55–48 47–40
Data Bus
D39–32 D31–24 D23–16
— — —
— — —
— — —
Data — —
7–0
— Data —
7–0
— — Data
7–0
— — —
— — —
— — —
Data — —
7–0
— Data Data
15–8 7–0
— — —
Data — —
7–0
— Data Data
31–24 23–16
Data Data Data
39–32 31–24 23–16
D15–8 D7–0
— —
— —
— —
— —
— —
— —
Data —
7–0
— Data
7–0
— —
— —
— —
Data Data
15–8 7–0
— —
Data Data
15–8 7–0
Data Data
15–8 7–0