Hitachi SH7750 series Hardware Manual page 463

Bus cycle
CPU
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode
Burst Mode: In burst mode, once the DMAC has acquired the bus it holds the bus and transfers
data continuously until the transfer end condition is satisfied. With '5(4 low level detection in
external request mode, however, when '5(4 is driven high the bus passes to another bus master
after the end of the DMAC transfer request that has already been accepted, even if the transfer end
condition has not been satisfied.
Figure 14.10 shows an example of DMA transfer timing in burst mode. The transfer conditions in
this example are single address mode and '5(4 level detection (CHCRn.DS = 0, CHCRn.TM =
1).
Bus cycle
CPU
Figure 14.10 Example of DMA Transfer in Burst Mode
Note: Burst mode can be set regardless of the data size. A 32-byte block transfer burst mode
setting can also be made.
Rev. 4.0, 04/00, page 452 of 850
CPU CPU DMAC
Read, write
CPU CPU DMAC
Bus returned to CPU
DMAC CPU DMAC
Read, write
DMAC DMAC DMAC
DMAC CPU CPU
DMAC DMAC CPU