Hitachi SH7750 series Hardware Manual page 803

TRr1
CKIO
t
A25–A0
t
t
RD/
t
t
CASD1
t
D63–D0
(write)
t
DACKn
(SA: IO ← memory)
t
DACKn
(SA: IO → memory)
Figure 23.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh (TRAS = 1, TRC = 1)
TRr2 TRr3
AD
CSD
RWD
t
RASD
RASD
t
CASD1
WDD
DACD
DACD
TRr4 TRr4w TRr5
t
RASD
t
CASD1
Trc Trc Trc
Rev. 4.0, 04/00, page 795 of 850