Hitachi SH7750 series Hardware Manual page 296

Superh risc engine

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Bits 28 to 26—Area 6 Burst Pitch (A6B2–A6B0): These bits specify the number of wait states to

be inserted from the second data access onward in a burst transfer.

Bit 28: A6B2

Bit 27: A6B1

Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait

states to be inserted for area 5.

Bit 25: A5W2

Bit 24: A5W1

Wait States Inserted

from Second Data

Bit 26: A6B0

Access Onward

7 (Initial value)

Bit 23: A5W0

Inserted Wait States

15 (Initial value)

Burst Cycle (Excluding First Cycle)

Rev. 4.0, 04/00, page 285 of 850

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