Hitachi SH7750 series Hardware Manual page 550

Superh risc engine
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Start
1
bit
Serial
0
D0
data
TDRE
TEND
TXI interrupt
request
Data written to SCTDR1
and TDRE flag cleared to
0 by TXI interrupt handler
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial
reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
Data
Parity
Stop
bit
bit
D1
D7
0/1
TXI interrupt
request
One frame
(Example with 8-Bit Data, Parity, One Stop Bit)
Start
Data
bit
1
0
D0
D1
Parity
Stop
bit
bit
Idle state
D7
0/1
1
(mark state)
TEI interrupt
request
Rev. 4.0, 04/00, page 539 of 850
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