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The read/write strobe signal address and &6 setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A3S0 and bits A3H1 and A3H0 in the WCR3
register.
When synchronous DRAM interface is set, the 5$6 and &$6 signals, RD/:5 signal, and byte
control signals DQM0 to DQM7 are asserted, and address multiplexing is performed. When
DRAM interface is set, the 5$6 signal, &$63 to &$6: signals, and RD/:5 signal are asserted,
and address multiplexing is performed. 5$6, &$6, and data timing control, and address
multiplexing control, can be set using the MCR register.
Area 4: For area 4, external address bits A28 to A26 are 100.
SRAM, MPX, and byte control SRAM can be set to this area.
A bus width of 8, 16, 32, or 64 bits can be selected with bits A4SZ1 and A4SZ0 in the BCR2
register. When MPX interface is set, a bus width of 32 or 64 bits should be selected with bits
A4SZ1 and A4SZ0 in the BCR2 register. When byte control SRAM interface is set, select a bus
width of 16, 32, or 64 bits. For details, see Memory Bus Width in section 13.1.5.
When area 4 is accessed, the &67 signal is asserted, and the 5' signal, which can be used as 2(,
and write control signals :(3 to :(:, are also asserted.
As regards the number of bus cycles, from 0 to 15 waits can be selected with bits A4W2 to A4W0
in the WCR2 register. In addition, any number of waits can be inserted in each bus cycle by means
of the external wait pin (5'<).
The read/write strobe signal address and &6 setup and hold times can be set within a range of 0–1
and 0–3 cycles, respectively, by means of bit A4S0 and bits A4H1 and A4H0 in the WCR3
register.
Area 5: For area 5, external address bits A28 to A26 are 101.
SRAM, MPX, burst ROM, and a PCMCIA interface can be set to this area.
When SRAM interface is set, a bus width of 8, 16, 32, or 64 bits can be selected with bits A5SZ1
and A5SZ0 in the BCR2 register. When burst ROM interface is set, a bus width of 8, 16 or 32 bits
can be selected with bits A5SZ1 and A5SZ0 in BCR2. When MPX interface is set, a bus width of
32 or 64 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. When a PCMCIA interface
is set, either 8 or 16 bits should be selected with bits A5SZ1 and A5SZ0 in BCR2. For details, see
Memory Bus Width in section 13.1.5.
When area 5 set is accessed with SRAM interface set, the &68 signal is asserted. In addition, the
5' signal, which can be used as 2(, and write control signals :(3 to :(:, are asserted. When a
PCMCIA interface is connected, the &(4$ and &(5$ signals, the 5' signal, which can be used
Rev. 4.0, 04/00, page 322 of 850
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