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SCI I/O port block diagrams are shown in figures 18.3 to 18.5.
MD0/SCK
Mode setting
register
SPTRR
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * Signals that set the SCK pin function as internal clock output or external clock input according to
the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1.
Rev. 4.0, 04/00, page 642 of 850
Reset
R
Q
SPB1IO
C
SPTRW
Reset
R
Q
SPB1DT
C
SPTRW
Figure 18.3 MD0/SCK Pin
D
Internal data bus
D
SCI
Clock output enable signal
Serial clock output signal
Serial clock input signal
Clock input enable signal
*
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