Section 14 Direct Memory Access Controller (Dmac); Overview; Features - Hitachi SH7750 series Hardware Manual

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Section 14 Direct Memory Access Controller (DMAC)

14.1

Overview

The SH7750 Series includes an on-chip four-channel direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed data transfers among external
devices equipped with DACK (DMA transfer end notification), external memories, memory-
mapped external devices, and on-chip peripheral modules (except the DMAC, BSC, and UBC).
Using the DMAC reduces the burden on the CPU and increases the operating efficiency of the
chip.
14.1.1

Features

The DMAC has the following features.
• Four channels
• Physical address space
• Choice of 8-bit, 16-bit, 32-bit, 64-bit, or 32-byte transfer data length
• Maximum of 16 M (16,777,216) transfers
• Choice of single or dual address mode
 Single address mode: Either the transfer source or the transfer destination (peripheral
device) is accessed by a DACK signal while the other is accessed by address. One data
transfer is completed in one bus cycle.
 Dual address mode: Both the transfer source and transfer destination are accessed by
address. Values set in DMAC internal registers indicate the accessed address for both the
transfer source and the transfer destination. Two bus cycles are required for one data
transfer.
• Channel functions: Transfer modes that can be set are different for each channel.
 Channel 0: Single or dual address mode. External requests are accepted.
Channel 1: Single or dual address mode. External requests are accepted.
 Channel 2: Dual address mode only.
 Channel 3: Dual address mode only.
• Transfer requests: The following three DMAC transfer activation requests are supported.
 External request: From two '5(4 pins. Either low level detection or falling edge detection
can be specified. External requests can be accepted on channels 0 and 1 only.
 Requests from on-chip peripheral modules: Transfer requests from the SCI, SCIF, and
TMU. These can be accepted on all channels.
 Auto-request: The transfer request is generated automatically within the DMAC.
Rev. 4.0, 04/00, page 419 of 850

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