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Single Write: The basic timing chart for write access is shown in figure 13.29. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data
is output at the same time as the write command. In the case of a write with auto-precharge,
precharging of the relevant bank is performed in the synchronous DRAM after completion of the
write command, and therefore no command can be issued for the same bank until precharging is
completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle
Trwl is also added as a wait interval until precharging is started following the write command.
Issuance of a new command for the same bank is postponed during this interval. The number of
Trwl cycles can be specified by bits TRWL2–TRWL0 in MCR.
As the SH7750 Series supports burst read/burst write operations for synchronous DRAM, there
are empty cycles in a single write operation.
Rev. 4.0, 04/00, page 357 of 850
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