Register Descriptions; Interrupt Priority Registers A To D (Ipra-Iprd) - Hitachi SH7750 series Hardware Manual

19.3

Register Descriptions

19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD)
Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for on-chip peripheral module interrupts. These registers are initialized
to H'0000 by a reset. They are not initialized in standby mode.
IPRA to IPRC
Bit: 15
Initial value: 0
R/W: R/W
Bit: 7
Initial value: 0
R/W: R/W
IPRD (SH7750S only)
Bit: 15
Initial value: 1
R/W: R/W
Bit: 7
Initial value: 0
R/W: R/W
Table 19.6 shows the relationship between the interrupt request sources and the IPRA–IPRD
register bits.
14 13
0 0
R/W R/W
6 5
0 0
R/W R/W
14 13
1 0
R/W R/W
6 5
1 1
R/W R/W
12 11
0 0
R/W R/W
4 3
0 0
R/W R/W
12 11
1 1
R/W R/W
4 3
1 0
R/W R/W
Rev. 4.0, 04/00, page 669 of 850
10 9
0 0
R/W R/W
2 1
0 0
R/W R/W
10 9
0 1
R/W R/W
2 1
1 0
R/W R/W
8
0
R/W
0
0
R/W
8
0
R/W
0
0
R/W