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(Z)
A
Ds
(Z)
A
Ds
17.3.5
Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with the bit rate register
(SCBRR1) and the CKS1 and CKS0 bits in the serial mode register (SCSMR1). The equation for
calculating the bit rate is shown below. Table 17.5 shows some sample bit rates.
If clock output is selected with CKE0 set to 1, a clock with a frequency of 372 times the bit rate is
output from the SCK pin.
B =
1488 × 2
Where: N = Value set in SCBRR1 (0 ≤ N ≤ 255)
B = Bit rate (bits/s)
Pφ = Peripheral module operating frequency (MHz)
n = 0 to 3 (See table 17.4)
Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings
n
0
1
2
3
Z
Z
A
D0
D1
D2
D3
(a) Direct convention (SDIR = SINV = O/ = 0)
Z
Z
A
D7
D6
D5
D4
(b) Inverse convention (SDIR = SINV = O/ = 1)
Figure 17.5 Sample Start Character Waveforms
φ P
× 10
× (N + 1)
2n–1
CKS1
0
0
1
1
Z
Z
Z
A
D4
D5
D6
A
A
A
A
D3
D2
D1
6
CKS0
0
1
0
1
A
Z
(Z)
State
D7
Dp
A
Z
(Z)
State
D0
Dp
Rev. 4.0, 04/00, page 623 of 850
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