Register Configuration - Hitachi SH7750 series Hardware Manual

Table 14.2 DMAC Pins in DDT Mode
Pin Name
Data bus request
Data bus available
Transfer request signal
DMAC strobe
Channel number
notification
14.1.4

Register Configuration

Table 14.3 summarizes the DMAC registers. The DMAC has a total of 17 registers: four registers
are allocated to each channel, and an additional control register is shared by all four channels.
Table 14.3 DMAC Registers
Chan-
nel Name
0 DMA source
address register 0
DMA destination
address register 0
DMA transfer
count register 0
DMA channel
control register 0
Abbreviation
'%5(4
('5(43)
%$9/
(DRAK0)
75
('5(44)
7'$&.
(DACK0)
ID [1:0]
(DRAK1, DACK1)
Abbre- Read/
viation Write
2
R/W*
SAR0
2
R/W*
DAR0
2
DMATCR0 R/W*
1,
R/W*
CHCR0
I/O Function
Input Data bus release request from external
device for DTR format input
Output Data bus release notification
Data bus can be used 2 cycles after
%$9/ is asserted
If asserted 2 cycles after %$9/
Input
assertion, DTR format is sent
Only 75 asserted: DMA request
'%5(4 and 75 asserted
simultaneously: Direct request to
channel 2
Output Reply strobe signal for external device
from DMAC
Output Notification of channel number to
external device at same time as 7'$&.
output
(ID [1] = DRAK1, ID [0] = DACK1)
Initial Value P4 Address
Undefined H'FFA00000 H'1FA00000 32
Undefined H'FFA00004 H'1FA00004 32
Undefined H'FFA00008 H'1FA00008 32
2
* H'00000000 H'FFA0000C H'1FA0000C 32
Rev. 4.0, 04/00, page 423 of 850
Area 7 Access
Address Size