Fifo Control Register (Scfcr2) - Hitachi SH7751 Hardware Manual

The SCBRR2 setting is found from the following equation.
Asynchronous mode:
φ P
N =
64 × 2
2n–1
Where B: Bit rate (bits/s)
N: SCBRR2 setting for baud rate generator (0

P : Peripheral module operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
n Clock
P

0
P
/4
1
P
/16
2
P
/64
3
The bit rate error in asynchronous mode is found from the following equation:
Error (%) =
16.2.9

FIFO Control Register (SCFCR2)

Bit: 15
—
Initial value: 0
R/W: R
Bit: 7
RTRG1
Initial value: 0
R/W: R/W
SCFCR2 performs data count resetting and trigger data number setting for the transmit and receive
FIFO registers, and also contains a loopback test enable bit.
SCFCR2 can be read or written to by the CPU at all times.
× 10
6
– 1
× B
CKS1
0
0
1
1
P × 10
φ 6
(N + 1) × B × 64 × 2
2n–1
14 13
— —
0 0
R R
6 5
RTRG0 TTRG1
0 0
R/W R/W
 
N 255)
SCSMR2 Setting
CKS0
0
1
0
1
– 1 × 100
12 11
— — RSTRG2 RSTRG1 RSTRG0
0 0
R R
4 3
TTRG0 MCE
0 0
R/W R/W
Rev. 3.0, 04/02, page 651 of 1064
10 9
0 0
R/W R/W
2 1
TFRST RFRST
0 0
R/W R/W
8
0
R/W
0
LOOP
0
R/W