Figure 13.55 Mpx Interface Timing 4 (Single Write, Anw = 1, One External Wait Inserted) - Hitachi SH7751 Hardware Manual

Tm1 Tmd1w Tmd1w Tmd1
CKIO
/
D31–D0
A
D0
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.55 MPX Interface Timing 4 (Single Write, AnW = 1, One External Wait
Inserted)
Rev. 3.0, 04/02, page 438 of 1064