Hitachi SH7751 Hardware Manual page 25

Figure 13.62 MPX Interface Timing 3
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)............................................................................. 445
Figure 13.63 MPX Interface Timing 4
(Burst Write Cycle, AnW = 1, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)............................................................................. 446
Figure 13.64 MPX Interface Timing 5
(Burst Read Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 447
Figure 13.65 MPX Interface Timing 6
(Burst Read Cycle, AnW = 0, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 448
Figure 13.66 MPX Interface Timing 7
(Burst Write Cycle, AnW = 0, No External Wait, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 449
Figure 13.67 MPX Interface Timing 8
(Burst Write Cycle, AnW = 1, External Wait Control, Bus Width: 32 Bits,
Transfer Data Size: 32 Bytes) .......................................................................... 450
Figure 13.68 Example of 52-Bit Data Width Byte Control SRAM....................................... 451
Figure 13.69 Byte Control SRAM Basic Read Cycle (No Wait) .......................................... 452
Figure 13.70 Byte Control SRAM Basic Read Cycle (One Internal Wait Cycle)................. 453
Figure 13.71 Byte Control SRAM Basic Read Cycle (One Internal Wait + One External
Wait) ................................................................................................................ 454
Figure 13.72 Waits between Access Cycles.......................................................................... 456
Figure 13.73 Arbitration Sequence ....................................................................................... 459
Figure 14.1 Block Diagram of DMAC................................................................................ 466
Figure 14.2 DMAC Transfer Flowchart.............................................................................. 485
Figure 14.3 Round Robin Mode.......................................................................................... 491
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode ........................ 492
Figure 14.5 Data Flow in Single Address Mode ................................................................. 494
Figure 14.6 DMA Transfer Timing in Single Address Mode ............................................. 495
Figure 14.7 Operation in Dual Address Mode .................................................................... 496
Figure 14.8 Example of Transfer Timing in Dual Address Mode....................................... 497
Figure 14.9 Example of DMA Transfer in Cycle Steal Mode............................................. 498
Figure 14.10 Example of DMA Transfer in Burst Mode ...................................................... 498
Figure 14.11 Bus Handling with Two DMAC Channels Operating ..................................... 502
Figure 14.12 Dual Address Mode/Cycle Steal Mode External Bus


Figure 14.13 Dual Address Mode/Cycle Steal Mode External Bus


Figure 14.14 Dual Address Mode/Burst Mode External Bus


Rev. 3.0, 04/02, page xxiv of xxxviii
(Level Detection), DACK (Read Cycle) .............................................. 505
(Edge Detection), DACK (Read Cycle) ............................................... 506
(Level Detection), DACK (Read Cycle) .............................................. 507

External Bus/

External Bus/

External Bus/