Exception Flow; Figure 5.2 Instruction Execution And Exception Handling - Hitachi SH7751 Hardware Manual

5.5

Exception Flow

5.5.1 Exception Flow
Figure 5.2 shows an outline flowchart of the basic operations in instruction execution and
exception handling. For the sake of clarity, the following description assumes that instructions are
executed sequentially, one by one. Figure 5.2 shows the relative priority order of the different
kinds of exceptions (reset/general exception/interrupt). Register settings in the event of an
exception are shown only for SSR, SPC, SGR, EXPEVT/INTEVT, SR, and PC, but other registers
may be set automatically by hardware, depending on the exception. For details, see section 5.6,
Description of Exceptions. Also, see section 5.6.4, Priority Order with Multiple Exceptions, for
exception handling during execution of a delayed branch instruction and a delay slot instruction,
and in the case of instructions in which two data accesses are performed.
Reset
requested?
No
Execute next instruction
General
exception requested?
No
Interrupt
requested?
No

Figure 5.2 Instruction Execution and Exception Handling

Yes
Is highest-
Yes
priority exception
re-exception
type?
No
Yes
SSR ← SR
SPC ← PC
SGR ← R15
EXPEVT/INTEVT ← exception code
SR.{MD,RB,BL} ← 111
PC ← (BRCR.UBDE=1 && User_Break?
DBR: (VBR + Offset))
Yes
Cancel instruction execution
result
EXPEVT ← exception code
SR. {MD, RB, BL, FD, IMASK} ← 11101111
PC ← H'A000 0000
Rev. 3.0, 04/02, page 125 of 1064