Figure 20.2 User Break Debug Support Function Flowchart - Hitachi SH7751 Hardware Manual

Hardware operation
EXPEVT ← exception code
Yes
PC ← DBR
Debug program
R15 ← SGR
(STC instruction)

Figure 20.2 User Break Debug Support Function Flowchart

Rev. 3.0, 04/02, page 772 of 1064
Exception
INTEVT ← interrupt code
No
(BRCR.UBDE == 1) &&
(user break exception)?
PC ← VBR + vector offset
Exception handling routine
Execute RTE instruction
Exception/interrupt
generation
SPC ← PC
SSR ← SR
SR.BL ← B'1
SR.MD ← B'1
SR.RB ← B'1
Exception/
interrupt/trap?
Interrupt
SGR ← R15
Reset exception?
No
PC ← SPC
SR ← SSR
End of exception
operations
Trap
EXPEVT ← H'160
TRA ← TRAPA (imm)
Yes
PC ← H'A0000000