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The MD10–MD0 pin values are input in the event of a power-on reset via the
Clock Modes
Table C.1
Clock Operating Modes (SH7751)
External
Pin Combination
Clock
Operating
Mode
MD2
MD1
0
0
0
1
2
1
3
4
1
0
5
Table C.2
Clock Operating Modes (SH7751R)
External
Pin Combination
Clock
Operating
Mode
MD2
MD1
0
0
0
1
2
1
3
4
1
0
5
6
1
Notes: 1. The multiplication factor of PLL1 is solely determined by the clock operating mode.
2. For the ranges input clock frequency, see the description of the EXTAL clock input
frequency (f
Signal Timing.
Appendix C Mode Pin Settings
1/2
Frequency
MD0
Divider
PLL1 PLL2
0
Off
On
1
Off
On
0
On
On
1
Off
On
0
On
On
1
Off
On
MD0
PLL1
0
On (
12) On
1
On (
12) On
0
On (
6)
1
On (
12) On
0
On (
6)
1
On (
12) On
0
OFF (
6) OFF
) and the CKIO clock output (f
EX
(vs. Input Clock)
CPU
Clock
On
6
On
6
On
3
On
6
On
3
On
6
Frequency
(vs. Input Clock)
CPU
Bus
PLL2
Clock
Clock
12
3
12
3/2
On
6
2
12
4
On
6
3
12
6
1
1/2
) in section 23.3.1, Clock and Control
OP
Rev. 3.0, 04/02, page 1041 of 1064
pin.
Frequency
Peripheral
Bus
Module
FRQCR
Clock
Clock
Initial Value
3/2
3/2
H'0E1A
1
1
H'0E23
1
1/2
H'0E13
2
1
H'0E13
3/2
3/4
H'0E0A
3
3/2
H'0E0A
Peripheral
FRQCR
Module Clock
Initial Value
3
H'0E1A
3/2
H'0E2C
1
H'0E13
2
H'0E13
3/2
H'0E0A
3
H'0E0A
1/2
H'0808
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