Figure 22.18 Peripheral Bus  Pci Bus Data Alignment; Table 22.10 Access Size - Hitachi SH7751 Hardware Manual

Table 22.10 Access Size

Access Destination
PCI external Memory space
device
I/O space
Configuration register
PCIC register
Notes: B: Byte
W: Word
LW: Longword
Memory/I/O space access (Peripheral bus ↔ PCI bus)
Peripheral bus
Size
Address
4n+0
4n+1
Byte
4n+2
4n+3
4n+0
Word
4n+2
Long
4n+0
Word
Figure 22.18 Peripheral Bus
Data (W/LW
Data
boundary mode)
31 0 31
B0
B1
B2
B3 B3
B0 B1
B2 B3 B2 B3
B0 B1 B2 B3 B0 B1 B2 B3
W/LW Boundary
Access Size Mode
B, W, LW Yes
B, W, LW Yes
LW Yes
LW Yes
PCI bus
Data (Byte data
boundary mode)
0 31
B0
B1
B2 B2
B3
B0 B1
B3 B2
B3 B2 B1 B0
 
PCI Bus Data Alignment
Transfer Mode
Byte Data
Boundary Mode
Yes
Yes
Yes
W/LW boundary
mode
Address
(memory I/O)
0
4n+0/4n+0
B0
B1 4n+0/4n+1
4n+0/4n+2
4n+0/4n+3
B1 B0 4n+0/4n+0
4n+0/4n+2
4n+0/4n+0
Rev. 3.0, 04/02, page 911 of 1064
1110
1101
1011
0111
1100
0011
0000