Pci Configuration Register 2 (Pciconf2) - Hitachi SH7751 Hardware Manual

Bit 0—I/O Space Control (IOS): Controls the access to the I/O space when the PCIC is
operating as a target. When this bit is 0, all I/O transfers to the PCIC are terminated by master
abort.
Bit 0: IOS
0
1
22.2.3

PCI Configuration Register 2 (PCICONF2)

Bit: 31
CLASS23 CLASS22 CLASS21 CLASS20 CLASS19 CLASS18 CLASS17 CLASS16
Initial value: —
PCI-R/W: R
PP Bus-R/W: R/W
Bit: 23
CLASS15 CLASS14 CLASS13 CLASS12 CLASS11 CLASS10 CLASS9 CLASS8
Initial value: —
PCI-R/W: R
PP Bus-R/W: R/W
Bit: 15
CLASS7 CLASS6 CLASS5 CLASS4 CLASS3 CLASS2 CLASS1 CLASS0
Initial value: —
PCI-R/W: R
PP Bus-R/W: R/W
Bit: 7
REVID7
Initial value:
*
PCI-R/W: R
PP Bus-R/W: R
*: Initial values vary with the logic versions of the chip.
The PCI configuration register 2 (PCICONF2) is a 32-bit read/partial-write register that includes
the class code and revision ID PCI configuration registers stipulated in the PCI local bus
Description
Disable access to I/O space
Enable access to I/O space
30 29
— —
R R
R/W R/W
22 21
— —
R R
R/W R/W
14 13
— —
R R
R/W R/W
6 5
REVID6 REVID5
* *
R R
R R
28 27
— —
R R
R/W R/W
20 19
— —
R R
R/W R/W
12 11
— —
R R
R/W R/W
4 3
REVID4 REVID3 REVID2
* *
R R
R R
Rev. 3.0, 04/02, page 817 of 1064
(Initial value)
26 25
— —
R R
R/W R/W R/W
18 17
— —
R R
R/W R/W R/W
10 9
— —
R R
R/W R/W R/W
2 1
REVID1 REVID0
* *
R R
R R
24
0
R
16
—
R
8
—
R
0
*
R
R