Figure 14.8 Example Of Transfer Timing In Dual Address Mode - Hitachi SH7751 Hardware Manual

CKIO
Transfer source Transfer destination
A28–A0
address address
D63–D0
DACK
Data read cycle Data write cycle
(1st cycle) (2nd cycle)
Transfer from external memory space to external memory space

Figure 14.8 Example of Transfer Timing in Dual Address Mode

Bus Modes
There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0–
CHCR3.
Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each
transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is
issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer.
At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end
condition is satisfied.
Cycle steal mode can be used with all categories of transfer request source, transfer source, and
transfer destination.
Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer


conditions in this example are dual address mode and level detection.
Rev. 3.0, 04/02, page 497 of 1064