Figure 22.23 Data Alignment At Target Configuration Transfer (Both Big Endian And Little Endian) - Hitachi SH7751 Hardware Manual

Target configuration read transfer data alignment (configuration register
Configuration register
31
B3 B2 B1 B0
SH7751 target configuration write transfer data alignment (PCI bus
Configuration register
31
B3 B2 B1 B0
SH7751R target configuration transfer data alignment (PCI bus
Configuration register
31
B3 B2 B1 B0
31
B3 B2 B1
31
B3 B2
31
B3 B2
31
B3
31
B3
31
B3
31
B3
31
B3
31
31
31
31
31
31
31
31
Figure 22.23 Data Alignment at Target Configuration Transfer
Rev. 3.0, 04/02, page 918 of 1064
0
0
0
0
0
B0
0
0
B1 B0
0
B1 B0
0
B1
0
B0
0
0
B2 B1 B0
0
B2 B1
0
B2 B0
0
B2
0
B1 B0
0
B1
0
B0
0
(Both Big Endian and Little Endian)
PCI bus
31 0
B3 B2 B1 B0
configuration register)
PCI bus
31 0
B3 B2 B1 B0
configuration register)
PCI bus
31 0
B3 B2 B1 B0
31 0
B3 B2 B1
31 0
B3 B2 B0
31 0
B3 B2
31 0
B3 B1 B0
31 0
B3 B1 B0
31 0
B3 B1
31 0
B3 B0
31 0
B3
31 0
B2 B1 B0
31 0
B2 B1
31 0
B2 B0
31 0
B2
31 0
B1 B0
31 0
B1
31 0
B0
31 0
PCI bus)
BE
H'0 to H'F
BE
H'0 to H'F
BE
0000
0001
0010
0011
0100
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111