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D.1
Pin States
Table D.1
Pin States in Reset, Power-Down State, and Bus-Released State
(PCI Enable, Disable Common)
Pin Name
I/O
D0–D31
I/O
A2–A17, A0–A25
O
I
/
O
/
I
O
CKE
O
–
O
O
/
O
RD/
O
I
/DQM3
O
/DQM2
O
/DQM1
O
/DQM0
O
/
O
/
O
O
/
O
DACK1–DACK0
O
MD7/CTS2
I/O
MD6/
I
MD5
I
MD4/
I/O*
MD3/
I/O*
Rev. 3.0, 04/02, page 1044 of 1064
Appendix D Pin Functions
Reset
(Power-On)
Master Slave
Master Slave
Z
Z
Z*
Z
Z
Z*
I
I
I
H
H
H
PI
PI
I*
H
PZ
H
H
H
O*
H
PZ
H
H
PZ
O*
H
PZ
O*
H
PZ
H
PI
PI
I*
H
PZ
O*
H
PZ
O*
H
PZ
O*
H
PZ
O*
H
PZ
O*
H
PZ
O*
H
PZ
O*
H
PZ
O*
L
L
L
19
19
I*
I*
I*
19
19
I*
I*
I*
19
19
I*
I*
Z*
2
19
19
I*
I*
Z*
3
19
19
I*
I*
Z*
Reset
(Manual)
Standby
16
16
16
Z*
Z*
15
9
15
15
7
O*
Z*
Z*
O*
I
I
H
H
14
14
14
I*
I*
15
15
7
Z*
Z*
H*
6
H
L
15
15
7
Z*
Z*
H*
6
15
15
5
Z*
Z*
O*
6
15
5
Z
Z*
O*
15
15
7
Z*
Z*
H*
14
14
14
I*
I*
6
15
15
5
Z*
Z*
O*
6
15
15
5
Z*
Z*
O*
6
15
15
5
Z*
Z*
O*
6
15
15
5
Z*
Z*
O*
6
15
15
5
Z*
Z*
O*
6
15
15
5
Z*
Z*
O*
6
15
15
5
Z*
Z*
O*
6
15
15
5
Z*
Z*
O*
13
8
L
Z*
O*
13
13
13
8
I*
I*
O*
14
14
14
I*
I*
15
15
15
Z*
Z*
15
15
15
7
H
Z*
Z*
H*
15
15
15
7
H
Z*
Z*
H*
Hard-
Bus
ware
Released
Standby Notes
16
Z*
Z
15
Z*
Z
I
I
O
Z
I
I
15
Z*
Z
6
O*
Z
15
Z*
Z
15
5
Z*
O*
Z
15
5
Z*
O*
Z
15
Z*
Z
14
I*
I
15
5
Z*
O*
Z
15
5
Z*
O*
Z
15
5
Z*
O*
Z
15
5
Z*
O*
Z
15
5
Z*
O*
Z
15
5
Z*
O*
Z
15
5
Z*
O*
Z
15
5
Z*
O*
Z
O
Z
DMAC
13
I*
O
Z
SCIF
14
I*
I
PCMCIA
(I/O)
15
Z*
Z
15
Z*
Z
PCMCIA
15
Z*
Z
PCMCIA
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