Table 21.3 Structure of Boundary Scan Register (cont)
No.
Pin name
239
AD25
238
AD25
237
AD25
236
AD26
235
AD26
234
AD26
233
AD27
232
AD27
231
AD27
230
AD28
229
AD28
228
AD28
227
AD29
226
AD29
225
AD29
224
AD30
223
AD30
222
AD30
221
AD31
220
AD31
219
AD31
218
217
216
215
214
213
212
211
210
PCICLK
Note: CTL is a low-active signal. The relevant pin is driven to the OUT state when CTL is set
LOW.
Rev. 3.0, 04/02, page 790 of 1064
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Type
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
CTL
OUT
IN