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Table 13.1 BSC Pins (cont)
Name
Signals
Column address
strobe 0
Column address
strobe 1
Column address
strobe 2
Column address
strobe 3
Ready
Area 0 MPX
MD6/
interface
specification/
16-bit I/O
Clock enable
CKE
Bus release
request
Bus use
permission
Area 0 bus
MD3/
width/PCMCIA
MD4/
card select
Endian switchover MD5
Master/slave
MD7/
switchover
DMAC0
DACK0
acknowledge
signal
DMAC1
DACK1
acknowledge
signal
I/O
Description
/DQM0
O
When setting DRAM interface:
D7–D0
When setting synchronous DRAM interface:
selection signal for D7–D0
/DQM1
O
When setting DRAM interface:
D15–D8
When setting synchronous DRAM interface:
selection signal for D15–D8
/DQM2
O
When setting DRAM interface:
D23–D16
When setting synchronous DRAM interface:
selection signal for D23–D16
/DQM3
O
When setting DRAM interface:
D31–D24
When setting synchronous DRAM interface:
selection signal for D31–D24
I
Wait state request signal
I
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
O
Synchronous DRAM clock enable control signal
/
I
Bus release request signal/bus acknowledge signal
/
O
Bus use permission signal/bus request
1
*
I/O
In power-on reset: area 0 bus width specification
signal
2
*
When using PCMCIA:
I
Endian specification in a power-on reset
I/O
Indicates master/slave status in a power-on reset
Serial interface
O
DMAC channel 0 data acknowledge
O
DMAC channel 1 data acknowledge
signal for
signal for
signal for
signal for
,
Rev. 3.0, 04/02, page 309 of 1064
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