Hitachi SH7751 Hardware Manual page 21

Figures
Figure 1.1 Block Diagram of SH7751 Series Functions ...................................................
Figure 1.2 Pin Arrangement (256-Pin QFP)......................................................................
Figure 1.3 Pin Arrangement (256-Pin BGA) ....................................................................
Figure 2.1 Data Formats....................................................................................................
Figure 2.2 CPU Register Configuration in Each Processor Mode ....................................
Figure 2.3 General Registers .............................................................................................
Figure 2.4 Floating-Point Registers...................................................................................
Figure 2.5 Data Formats In Memory.................................................................................
Figure 2.6 Processor State Transitions ..............................................................................
Figure 3.1 Role of the MMU.............................................................................................
Figure 3.2 MMU-Related Registers ..................................................................................
Figure 3.3 Physical Address Space (MMUCR.AT = 0) ....................................................
Figure 3.4 P4 Area ............................................................................................................
Figure 3.5 External Memory Space...................................................................................
Figure 3.6 Virtual Address Space (MMUCR.AT = 1) ......................................................
Figure 3.7 UTLB Configuration........................................................................................
Figure 3.8 Relationship between Page Size and Address Format .....................................
Figure 3.9 ITLB Configuration .........................................................................................
Figure 3.10 Flowchart of Memory Access Using UTLB ....................................................
Figure 3.11 Flowchart of Memory Access Using ITLB......................................................
Figure 3.12 Operation of LDTLB Instruction .....................................................................
Figure 3.13 Memory-Mapped ITLB Address Array ...........................................................
Figure 3.14 Memory-Mapped ITLB Data Array 1..............................................................
Figure 3.15 Memory-Mapped ITLB Data Array 2..............................................................
Figure 3.16 Memory-Mapped UTLB Address Array..........................................................
Figure 3.17 Memory-Mapped UTLB Data Array 1 ............................................................
Figure 3.18 Memory-Mapped UTLB Data Array 2 ............................................................
Figure 4.1 Cache and Store Queue Control Registers (CCR)............................................
Figure 4.2 Configuration of Operand Cache (SH7751) ....................................................
Figure 4.3 Configuration of Operand Cache (SH7751R)..................................................
Figure 4.4 Configuration of Write-Back Buffer................................................................
Figure 4.5 Configuration of Write-Through Buffer ..........................................................
Figure 4.6 Configuration of Instruction Cache (SH7751) ................................................. 100
Figure 4.7 Configuration of Instruction Cache (SH7751R) .............................................. 101
Figure 4.8 Memory-Mapped IC Address Array ................................................................ 104
Figure 4.9 Memory-Mapped IC Data Array...................................................................... 105
Figure 4.10 Memory-Mapped OC Address Array .............................................................. 106
Figure 4.11 Memory-Mapped OC Data Array .................................................................... 107
Figure 4.12 Memory-Mapped IC Address Array ................................................................ 109
Figure 4.13 Memory-Mapped IC Data Array...................................................................... 110
Figure 4.14 Memory-Mapped OC Address Array .............................................................. 111
Figure 4.15 Memory-Mapped OC Data Array .................................................................... 112
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