Pin Configuration; Table 13.1 Bsc Pins - Hitachi SH7751 Hardware Manual

13.1.3

Pin Configuration

Table 13.1 shows the BSC pin configuration.

Table 13.1 BSC Pins

Name Signals
Address bus A25–A0
Data bus D31–D0


Bus cycle start

Chip select 6–0
Read/write RD/

Row address
strobe
Read/column

address strobe/
cycle frame

Data enable 0

Data enable 1

Data enable 2

Data enable 3
Rev. 3.0, 04/02, page 308 of 1064
I/O
O
I/O
O

O
–
O
O
 
/ / O

/ O
O

/ O

/ O
Description
Address output
Data input/output
Signal that indicates the start of a bus cycle
When setting synchronous DRAM interface or MPX
interface: asserted once for a burst transfer
For other burst transfers: asserted each data cycle
Chip select signals that indicate the area being
accessed
 
and are also used as PCMCIA


Data bus input/output direction designation signal
Also used as the DRAM/synchronous
DRAM/PCMCIA interface write designation signal

signal when setting DRAM/synchronous DRAM
interface
Strobe signal that indicates a read cycle
When setting synchronous DRAM interface:
signal
When setting MPX interface:
When setting PCMCIA interface:
When setting SRAM interface: write strobe signal for
D7–D0
When setting PCMCIA interface: write strobe signal
When setting SRAM interface: write strobe signal for
D15–D8
When setting PCMCIA interface:
When setting SRAM interface: write strobe signal for
D23–D16
When setting PCMCIA interface:
When setting SRAM interface: write strobe signal for
D31–D24

and
 

signal

signal

signal

signal