Table 5.3 Types Of Reset - Hitachi SH7751 Hardware Manual

(2) Manual Reset


Sources:



pin low level and

When a general exception other than a user break occurs while the BL bit is set to 1 in SR

When the watchdog timer overflows while the RSTS bit is set to 1 in WTCSR. For details,
see section 10, Clock Oscillation Circuits.


Transition address: H'A000 0000


Transition operations:
Exception code H'020 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask bits (I3–I0) are
set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections.
Manual_reset()
{
EXPEVT = H'00000020;
VBR = H'00000000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.(I0-I3) = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(Manual);
PC = H'A0000000;
}
Table 5.3 Types of Reset
Type
Power-on reset
Manual reset
Rev. 3.0, 04/02, page 130 of 1064


Reset State Transition
Conditions

 

 
— Low
Low High
pin high level
CPU
Initialized
Initialized
Internal States
On-Chip Peripheral
Modules
See Register
Configuration in
each section