Port Data Register A (Pdtra); Port Control Register B (Pctrb) - Hitachi SH7751 Hardware Manual

Bit 2n (n = 0–15)—Port I/O Control (PBnIO): Specifies whether each bit in the 16-bit port A is
an input or an output.
Bit 2n: PBnIO
0
1
18.2.2

Port Data Register A (PDTRA)

Port data register A (PDTRA) is a 16-bit readable/writable register used as a data latch for each bit
in the 16-bit port A. When a bit is set as an output, the value written to the PDTRA register is
output from the external pin. When a value is read from the PDTRA register while a bit is set as an
input, the external pin value sampled on the external bus clock is read. When a bit is set as an
output, the value written to the PDTRA register is read.
PDTR is not initialized by a power-on or manual reset, or in standby mode, and retains its
contents.
Bit: 15
PB15DT PB14DT PB13DT PB12DT PB11DT PB10DT
Initial value: —
R/W: R/W
Bit: 7
PB7DT
Initial value: —
R/W: R/W
18.2.3

Port Control Register B (PCTRB)

Port control register B (PCTRB) is a 32-bit readable/writable register that controls the input/output
direction and pull-up for each bit in the 16-bit port B (port 31 pin to port 16 pin). As the initial
value of port data register B (PDTRB) is undefined, each bit in the 16-bit port B should be set to
output with PCTRB after writing a value to the PDTRB register.
PCTRB is initialized to H'00000000 by a power-on reset. It is not initialized by a manual reset or
in standby mode, and retains its contents.
Rev. 3.0, 04/02, page 720 of 1064
Description
Bit m (m = 0–15) of 16-bit port A is an input
Bit m (m = 0–15) of 16-bit port A is an output
14 13
— —
R/W R/W
6 5
PB6DT PB5DT
— —
R/W R/W
12 11
— —
R/W R/W
4 3
PB4DT PB3DT PB2DT
— —
R/W R/W
(Initial value)
10 9
PB9DT PB8DT
— —
R/W R/W R/W
2 1
PB1DT PB0DT
— —
R/W R/W R/W
8
—
0
—