Figure 23.34(B) Synchronous Dram Bus Cycle: Mode Register Setting (Set) - Hitachi SH7751 Hardware Manual

TRp1
CKIO
t
Bank
Precharge-sel
Address
t
RD/
t
t
t
DQMn
t
D31–D0
(write)
CKE
t
DACKn
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high

Figure 23.34(b) Synchronous DRAM Bus Cycle: Mode Register Setting (SET)

Rev. 3.0, 04/02, page 990 of 1064
TRp2 TRp3 TRp4
AD
RWD
RASD
t
CASD2 CASD2
DQMD
WDD
DACD
TMw TMw2 TMw3
t
AD
t t
CSD CSD
t
RWD
t
RASD
t
CASD2
TMw4 TMw5
t
AD
t
CSD
t
RWD
t
RASD
t
CASD2
t
DQMD
t
WDD
t
BSD
t
DACD