Table D.2 Pin States In Reset, Power-Down State, And Bus-Released State (Pci Enable) - Hitachi SH7751 Hardware Manual

Table D.2 Pin States in Reset, Power-Down State, and Bus-Released State (PCI Enable)
Pin Name I/O
AD31–AD31 I/O
 
– I/O
PAR I/O



I/O



I/O

I/O

I/O

I/O


I/O


I/O


I/O

 
– I/O

 

 
/ I
 
 
– O
 
 
/ O

  
PCICLK I


O
IDSEL I
 
O
Rev. 3.0, 04/02, page 1046 of 1064
Reset Reset
(Power On) (Manual)
Non-
Host Host Host
L Z IOZ
L Z IOZ
L Z IOZ
12
PZ PZ IOZ*
12
PZ PZ IOZ*
12
PZ PZ IZ*
12
PZ PZ IOZ*
12
PZ PZ IOZ*
12
PZ PZ IOZ*
12
PZ PZ IOZ*
12
PZ PZ IOZ*
12
PI PZ I*
12
PI PI I*
Z Z O
Z Z O
I I I
L L K
PI I PI
PZ PZ ODK
12
*
Standby
Non- Non-
Host Host Host
IOZ K Z
IOZ K Z
IOZ K Z
12 12 12
IOZ* Z* Z*
12 12 12
IOZ* Z* Z*
12 12 12
IZ* Z* Z*
12 12 12
IOZ* Z* Z*
12 12 12
IOZ* Z* Z*
12 12 12
IOZ* Z* Z*
12 12 12
IOZ* Z* Z*
12 12 12
IOZ* Z* Z*
12 12 12
Z* I* Z*
13, 18 12,
(IO* * ) (IO* *
12 12 12
I* I* I*
Z K Z
(K) (K)
O K K
I I I
K K K
I PI I
12
ODK * ODK ODK *
12
*
Reset
(Software)
Hard-
Non- ware
Host Host Standby Notes
L Z Z
L Z Z
L Z Z
PZ PZ Z
PZ PZ Z
PZ PZ Z
PZ PZ Z
PZ PZ Z
PZ PZ Z
PZ PZ Z
PZ PZ Z
PI PZ Z
18 12, 18
) (IO* * )
PI PI Z
Z Z Z
(K)
Z H Z
I I Z
L L Z
PI I Z
12
PZ PZ Z
Values
in paren-
thesis
are
when
using
PORT
Values
in paren-
thesis
are
when
using
PORT