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Table D.3
Pin States in Reset, Power-Down State, and Bus-Released State (PCI Disable)
Pin Name
AD31–AD0
–
PAR
–
–
PCICLK
IDSEL
Notes: I:
Input
O:
Output
H:
High-level output
L:
Low-level output
Z:
High-impedance
K:
Output state held
IZ/IOZ: Response to access from PCI
PZ:
Pulled up with a built-in pull-up resistance
PI:
Input pulled up with a built-in pull-up resistance
ODK:
Open-drain output state held
Reset
(Power-On)
I/O
Master Slave
I/O
Z
Z
—
Z
Z
O
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
—
Z
Z
O
Z
Z
O
Z
Z
—
Z
Z
O
Z
Z
—
Z
Z
—
Z
Z
Reset
(Manual)
Master Slave
Standby
17
Z
Z
Z*
(K)
(K)
(K)
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Rev. 3.0, 04/02, page 1047 of 1064
Hard-
Bus
ware
Released
Standby Notes
17
Z*
Z
Values
(K)
in paren-
thesis
are
when
using
PORT
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
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