Figure 23.19 Burst Rom Bus Cycle (No Wait, Address Setup/Hold Time Insertion, Ans = 1, Anh = 1) - Hitachi SH7751 Hardware Manual

Superh risc engine
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Figure 23.19 Burst ROM Bus Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1)
Rev. 3.0, 04/02, page 974 of 1064

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