Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword, Quadword/External Device  External Bus Data Transfer - Hitachi SH7751 Hardware Manual

CKIO
DBREQ
BAVL
TR
A25–A0
D31–D0
CMD
DQMn
TDACK
ID1, ID0
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device
Rev. 3.0, 04/02, page 540 of 1064
CA
D0
DTR
WT
CA
D1
WT
Idle cycle Idle cycle
 
External Bus Data Transfer
CA
D3
WT
Idle cycle