Synchronous Dram Mode Register (Sdmr) - Hitachi SH7751 Hardware Manual

Bit 5: A5TEH2
0
1
Bits 2 to 0—OE/WE Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address
hold delay time from
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 2: A6TEH2
0
1

13.2.10 Synchronous DRAM Mode Register (SDMR)

The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is
written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3
synchronous DRAM.
Settings for the SDMR register must be made before accessing synchronous DRAM.
Rev. 3.0, 04/02, page 352 of 1064
Bit 4: A5TEH1
0
1
0
1
 
/ negation in a write on the connected PCMCIA interface or in an I/O
Bit 1: A6TEH1
0
1
0
1
Bit 3: A5TEH0
0
1
0
1
0
1
0
1
Bit 0: A6TEH0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15