Hitachi SH7751 Hardware Manual page 14

14.4.1 Examples of Transfer between External Memory and an External Device
with DACK .......................................................................................................... 519
14.5 On-Demand Data Transfer Mode (DDT Mode) ................................................................ 520
14.5.1 Operation.............................................................................................................. 520
14.5.2 Pins in DDT Mode ............................................................................................... 522
14.5.3 Transfer Request Acceptance on Each Channel................................................... 525
14.5.4 Notes on Use of DDT Module ............................................................................. 547
14.6 Configuration of the DMAC (SH7751R) .......................................................................... 550
14.6.1 Block Diagram of the DMAC .............................................................................. 550
14.6.2 Pin Configuration (SH7751R).............................................................................. 551
14.6.3 Register Configuration (SH7751R)...................................................................... 552
14.7 Register Descriptions (SH7751R) ..................................................................................... 555
14.7.1 DMA Source Address Registers 0-7 (SAR0-SAR7)........................................... 555
14.7.2 DMA Destination Address Registers 0-7 (DAR0-DAR7) .................................. 555
14.7.3 DMA Transfer Count Registers 0-7 (DMATCR0-DMATCR7) ......................... 556
14.7.4 DMA Channel Control Registers 0-7 (CHCR0-CHCR7) ................................... 556
14.7.5 DMA Operation Register (DMAOR) ................................................................... 559
14.8 Operation (SH7751R)........................................................................................................ 562
14.8.1 Channel Specification for a Normal DMA Transfer ............................................ 562
14.8.2 Channel Specification for DDT-Mode DMA Transfer ........................................ 562
14.8.3 Transfer Channel Notification in DDT Mode ...................................................... 562
14.8.4 Clearing Request Queues by DTR Format ........................................................... 563
14.8.5 Interrupt-Request Codes....................................................................................... 564
14.9 Usage Notes....................................................................................................................... 567
Section 15 Serial Communication Interface (SCI)
15.1 Overview ........................................................................................................................... 569
15.1.1 Features ................................................................................................................ 569
15.1.2 Block Diagram ..................................................................................................... 571
15.1.3 Pin Configuration ................................................................................................. 572
15.1.4 Register Configuration ......................................................................................... 572
15.2 Register Descriptions......................................................................................................... 573
15.2.1 Receive Shift Register (SCRSR1) ........................................................................ 573
15.2.2 Receive Data Register (SCRDR1)........................................................................ 573
15.2.3 Transmit Shift Register (SCTSR1)....................................................................... 574
15.2.4 Transmit Data Register (SCTDR1) ...................................................................... 574
15.2.5 Serial Mode Register (SCSMR1) ......................................................................... 575
15.2.6 Serial Control Register (SCSCR1) ....................................................................... 577
15.2.7 Serial Status Register (SCSSR1) .......................................................................... 581
15.2.8 Serial Port Register (SCSPTR1)........................................................................... 585
15.2.9 Bit Rate Register (SCBRR1) ................................................................................ 589
15.3 Operation........................................................................................................................... 597
15.3.1 Overview .............................................................................................................. 597
..................................................... 569
Rev. 3.0, 04/02, page xiii of xxxviii