I/O Space Base Register (Pciiobr) - Hitachi SH7751 Hardware Manual

Bits 31 to 24—Memory Space Base Address (MBR31 to 24): Sets the base address for the PCI
memory space in PIO transfers. (Initial value is undefined.)
Bits 23 to 1—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Bit 0—Lock Transfer (LOCK): Specifies the locking of the memory space during PIO transfer.
Bit 0: LOCK
0
1

22.2.34 I/O Space Base Register (PCIIOBR)

Bit: 31
IOBR31
Initial value: 0
PCI-R/W: —
PP Bus-R/W: R/W
Bit: 23
IOBR23
Initial value: 0
PCI-R/W: —
PP Bus-R/W: R/W
Bit: 15
—
Initial value: 0
PCI-R/W: —
PP Bus-R/W: R
Bit: 7
—
Initial value: 0
PCI-R/W: —
PP Bus-R/W: R
Rev. 3.0, 04/02, page 868 of 1064
Description
Not locked
Locked
30 29
IOBR30 IOBR29
0 0
— —
R/W R/W
22 21
IOBR22 IOBR21
0 0
— —
R/W R/W
14 13
— —
0 0
— —
R R
6 5
— —
0 0
— —
R R
28 27
IOBR28 IOBR27
0 0
— —
R/W R/W
20 19
IOBR20 IOBR19
0 0
— —
R/W R/W
12 11
— —
0 0
— —
R R
4 3
— —
0 0
— —
R R
(Initial value)
26 25
IOBR26 IOBR25 IOBR24
0 0
— —
R/W R/W
18 17
IOBR18 —
0 0
— —
R/W R
10 9
— —
0 0
— —
R R
2 1
— —
0 0
— —
R R
24
0
—
R/W
16
—
0
—
R
8
—
0
—
R
0
LOCK
0
—
R/W