Figure 22.37 Dram Bus Cycles (1) Rcd[1:0] = 00, Anw[2:0] = 000, Tpc[2:0] = 001 (2) Rcd[1:0] = 01, Anw[2:0] = 001, Tpc[2:0] = 010 - Hitachi SH7750 Hardware Manual

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Figure 22.37 DRAM Bus Cycles

(1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001

(2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010

Rev. 6.0, 07/02, page 900 of 986

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