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MACHINE INSTRUCTIONS AND __
STACK OPERATIONS
I
IV
I
This section contains information' on the computer system's
basic
instruction set
and
describes
representative instructions
for
most of the 13
instruction groups and how some of these instruc-
tions
affe~t
stack operations.
For complete descriptions of all
the
machine instructions,
including
extended instruction
sets
refer to
the HP 3000
Series II/III Computer
System Machine In-
struction Set Manual, part no. 30000-90022.
4-1. INSTRUCTION DECODING
As the CPU executes a user program, it fetches the
required
ma-
chine
instructions from memory.
A ROM address of a microprogram
stored in a microprogram ROM is generated for
the
instructions.
There
is
a microp rogr am in ROM for each of the machine instr uc-
tions.
The ROM address is stored in
the
ROM
Address
Register
(RAR).
The RAR is used first to access the initial microinstruc-
tion and is then incremented to point to the
next
microinstruc-
tion.
Thus,
the
entire microprogram for a particular machine
instruction is called and executed by the
CPU
as
discussed
in
Section I I •
4-2. TRAPS AND INTERRUPTS
Only those traps and interrupts which occur as a
result
of
in-
struction execution over which the user has some control are used
in the instruction descriptions provided in this
section.
They
are
defined
here
by
segment
#1
Segment Transfer Table (STT)
number.
a.
STT #1; BNDV - Bounds Violation.
is outside of the legal
bounds
addressing.
An operand
or
instruction
for
a
particular
mode
of
b.
STT #17; STTV - Segment Transfer Table Violation.
A
variety
of conditions can force this trap as follows:
(1)
The STT
number in an external progam
label is
greater
than the
STT length pointed to by
PL in the referenced
segment.
Thi$ error can occur in PCAL,
LLBL,
and the
firmware interrupt handler while
attempting to set up a
new segme nt .
(2)
In LLBL,
the label fetched
from
PL-N
is
an internal
label
and N is greater than 128 (%177).
This would re-
quire too large an STT number when creating the external
label.
4-1
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