HP 3000 III Series Manual page 320

Inte rrupt System
Interrupt Handler loads a parameter onto the stack. The parame-
ter (listed in table 8-1) passes information regarding the inter-
rupt from the hardware to the interrupt processing software.. In
some cases, the parameter is simply an interrupt identifica tion
number; in other cases, the parameter gives specific information,
such as a program label, to the interrupt routine.
8-13. General Descriptions
8-14. BOUNDS VIOLATION. A bounds violation trap is caused by
attempting to address locations outside of a specified program
dana in or data dana in. (Refer to paragr aph 2-65.)
8-15. ILLEGAL MEMORY ADDRESS. A memory address interrupt is
caused by attempting to access a word of memory that does not
phys ically exi st on the system.
8-16. NON-RESPONDING MODULE. A non-responding module interrupt
occurs when the CPU requests information from some other module
and that information is not received in a reasonable length of
time (a preset time on the order of 4.6 milliseconds).
8-17. SYSTEM PARITY ERROR. A parity error is detected on the
8-bit system information (TO, FROM, COMMAND) transmitted by the
CPU to memory, or by memory to the CPU. This error will also be
generated in the case where the CPU is waiting for data and a
Memory-to-IOP transmission takes place with bad parity. In this
case a transfer error is also sent to the requesting device.
Note that the converse is also true (i.e., if the lOP is waiting
for data and the CPU receives a transmission with bad system par-
ity, a transfer error is sent to the requesting device). The
above is the resul t of the CPU and lOP shar ing the same module
number. A system parity error also results if any module sends
data with bad parity (not addresses) to
~emory.
8-18. ADDRESS PARITY ERROR. A parity error is detected by the
memory on the 16-bit address word sent to it from any module.
Upon detection of the error, the memory sends an appropriate er-
ror signal back to the CPU and prevents the word addressed from
be ing al te red.
8-19. DATA PARITY ERROR. A parity error is detected by the CPU
on the 16-bit data word sent to it from the memory. When a par i-
ty error is detected on a memory transmission, the appropriate
bi t is set in CPXl (the CPU sta tus word for RUN-mode interrupts)
and the instruction runs to completion (with the exception of
certain interruptable instructions such as the group of move in-
structions). The result of the instruction is normally meaning-
less. If the parity error is due to a CPU read cycle (outgoing
system or address information or incoming data), it is possible
that the received data will be used by the CPU as an address for
a follow ing wr ite cycle. In this case it would be possible to
store erroneous data at some location. However, since bounds
checking is done on the address, the worst that can happen is the
destruction of a memory location in the current user's stack (as-
8-14