Mach Ine Re Giste Rs - HP 3000 III Series Manual

Sys tern/CPU Overview
Table 2-3. Mach ine Re giste rs
PB
P
PL
PB-Bank
CIR
NIR
DL
DB
Q
SM
SR
Z
DB-Bank
S-Bank
RA
RB
RC
RD
x
Code Segment
Pointers
Next Instruction
Register
Da ta Segment
(Stack) Pointers
Top Of Stac k (TOS)
Registers
Index Register
SPO
SPI
SP2
SP3
CTR
ABS-Bank
CPXl
CPX2
MOD
lOA
laD
ACOR
DCOR
OPND
RAR
SAVE
STA
Process Clock
Register
Scratch Pad, Flag,
and Inte rrupt
Registers
I/O Re g is te r s
Memory Address and
Da ta Registers
Firmware Address
Registers
Status Register
2-22. CODE SEGMENT REGISTERS. The functions of the CPU code
segment registers are as follows:
The PB Register defines the program base of the code segment be-
ing executed. The PB Register contains a 16-bit absolute address
pointing to the first memory location of the code segment.
The PB-Bank Register is a 4-bit register used in conjunction with
the PB Register to define in which memory bank the code segment
res ides.
The PL Register defines the program limit of the code segment
being executed. The PL Register contains a 16-bit absolute ad-
dress pointing to the last memory location of the code segment.
The P Register is the program counter. The P Register contains a
16-bit absolute address pointing to the memory location of the
instruction being executed. The P Register can never point to a
location beyond the limits defined by the PB and PL Registers.
2-12