HP 3000 III Series Manual page 77

System/CPU Overview
2-66. PROGRAM TRANSFER LIMIT. Program control cannot be passed
to any location beyond the limits defined by the contents of the
PB and PL Registers. For indirect branches, both the indirect and
direct references must be within limits. This also applies when
branching indirect via the data stack, except that the initial
reference must be within data stack limits DB and S rather than
code segment limits PB and PL.
2-67. PROGRAM REFERENCE LIMITS. Some of the Memory Address in-
str uctions, all wop Control instr uctions, and some ~ve instr uc-
tions are capable of addressing locations in the code segment.
During privileged mode, these references can be made as desired.
During non-privileged user mode however, these references (both
direct and indirect) must be within the limits defined by PB and
PL.
2-68. DATA REFERENCE LIMITS. During privileged mode, data ref-
erences are not sUbject to bounds checking. During non-privileged
user mode however, these references (both direct and indirect)
must be within the user's area defined by DL and S.
2-69. STACK OVERFLOW LIMIT. Stack overflow is defined as moving
the S-pointer beyond the stack limit. Stack overflow occurs when
SM exceeds Z. Since SM is not necessarily the actual TOS (SM may
equal S or be up to four locations lower) and to allow marker
space for the remote possibility of a procedure call and an in-
terrupt while SM is at
Z,
there is a zone of approximately 128
locations beyond
Z
which could be filled with stack related data.
A stack overflow causes an interrupt which, under discretion of
the operating system, may extend the stack limit.
2-70. STACK UNDERFLOW LIMIT. Stack underflow is defined as mov-
ing the S-pointer below the data base or, more strictly, moving
SM below DB. Since SM may not equal S, underflow can occur even
though S is up to three locations above DB. During privileged
mode, stack underflow is not subject to checking. During non-
privileged user mode however, stack underflow will cause an in-
terrupt. Users can accebS the area between DL and DB by indirect
addressing or indexing (paragraph 2-62) as long as SM does not
become less than DB. Although the hardware does address arithme-
tic modulo 64K, code segments and data stacks can not cross mem-
ory bank boundries. This restriction is handled by the operating
system.
2-71. CPU DVE RVI EW
Operation of the CPU is controlled by the software set of in-
structions and the microprogram. Logically, the CPU (figure
2-20) consists of three sections; a microprocessor, processor
registers, and an arithmetic logic unit (ALU). The microproces-
sor receives an instruction word from Main Memory and translates
it into a microprogram starting address. The microprogram is
then read out of read-only memory (ROM) and is decoded into a set
sequence of control signals. The processor registers are flip-
flop registers that can be loaded from the U-Bus (i.e., output of
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