HP 3000 III Series Manual page 162

Machine Instructions and Stack Operations
In step 5, if in user mode, the privileged bit in the CST entry
for the return segment must be off. (Although not shown, the ref-
erence bit in the CST entry is set at this time for statistical
purposes. )
An absent code segment trap occurs following step 5 if the return
segment is absent. A trace trap occurs in step
6
if bit
0
of
Delta P in the marker is set. This bit is normally set by the
trace routine which would have been called when the current pro-
cedure was entered.
At step 7, return "P
=
P-Del ta P" from the marker must be between
PB and PL. The Status Register is restored from the marker; Q is
set pointing to the previous marker, then S is decremented by
4
to delete the marker on the top of the stack and by N (specified
in the EXIT instruction) to delete any parameters passed to the
procedure being exited. P is set to return P and execution be-
gins within the return procedure.
7. DISP, IXIT, PSDB, PSEB. The Dispatcher, external interrupts,
and some internal interrupts execute on the Interrupt Control
Stack (ICS). Normally the Dispatch (DISP) instruction is used to
enter the Dispatcher and the Interrupt Exit (IXIT) is used to
exit from the Dispatcher. Also, when "ICS" type interrupt ser-
vice routines are entered in response to appropriate events, the
instruction IXIT is used to exit from these. The exit may be
from the Dispatcher to the process being launched or from inter-
rupt service routines to the interrupted procedure or, in certain
cases, to the Dispatcher entry point. The instructions Pseudo
Interrupt Disable (PSDB) and Pseudo Interrupt Enable (PSEB) are
used to prevent entry to the Dispatcher during critical sections
of code.
The instruction DISP causes a transfer to the Dispatcher's entry
point unless it is executed while on the ICS or while the Dis-
patcher is disabled. The Dispatcher is disabled when the Dis-
patcher Flag is non-zero, (QI-18) not
O.
The address of Ql is
located at 4 times the CPU number plus 1. Condition code CCE is
set when the Dispatcher is entered; the Status Register is set as
specified for the Dispatcher. The transfer is executed in a
manner similar to an ICS interrupt. If a DISP instruction is
executed on the ICS or while the Dispatcher is disabled, bit 0 of
(QI) is set and CCG is set in the Status Register. This bit is
checked by those instructions (IXIT and PSEB) which may remove
the conditions inhibiting the Dispatcher.
The instruction PSDB increments (QI-18); PSEB decrements (QI-18).
Starting the Dispatcher is disabled unless this location is zero.
Outside the Dispatcher and not on the lCS, a PSEB which decre-
ments (QI-18) to zero effectively does a DISP instruction if bit
o
of (QI) is set.
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