HP 3000 III Series Manual page 64

System/CPU Overview
Bit 3 is normally used only by the hardware which sets this bit
to 1 if the right stack opcode (bits 10 through 15) contains a
valid instruction other than NOP. The hardware requires this
information in case an interrupt occurs between the execution of
the left and right stack ops. The state of bit 3 cannot be
changed in user mode while current.
Bit 4 is the overflow bit and is one of the three indicators
which are set or cleared as an incidental operation by many of
the machine instructions. In general, bit 4 is used only by
signed integer and floating-point computa tions. If bi t 4 is se t
(1), it indicates that the result of the computation is too large
to be represented in the number of available bits in the data
format. (For floating point, it can also indica·te that the resul t
is too small.) If user traps are enabled (bit 2
=
1), an inter-
rupt to segment 1 will occur in lieu of setting bit 4; except for
integer overflow which causes both bit 4 to be set and an inter-
r up t to s e
grn
ent 1. Th i s pe rm i ts the s
ys
te rn tog e ne rate a me s sag e
to the user which indicates which type of overflow or underflow
occurred. All user traps will set bit 4 if traps are disabled.
Bit 5 is the carry bit and is one of the three indicators which
are se t or cleared as an incidental opera tion by many of the
machine instructions. Bit 5 is used primarily by logical and
integer arithmetic and usually indicates a carry (bit 5 =1) or
lack of carry (bit 5
=
1) out of the most significant bit during
a computation. Bit 5 is also used by some instructions as an
indicator for special purposes which are stated in the individual
machine instruction definitions. (Refer to section IV.)
Bits 6 and 7 are used to encode the condition codes discussed in
paragraph 2-46 and are one of the three indicators which are set
or cleared as an incidental operation by many of the machine
instr uctions.
2-46. Condition Codes
Although several instructions make special use of the condition
code bits (status word bits 6 and 7), the condition code typi-
cally ind ica tes the s ta te of an operand or a compar ison res ul t
with two operands. The ope rand can be a word, byte, double word,
or tr iple word and can be loca ted on the TOS, in the X Registe r ,
or in a specified memory location. Three codings are used; 00,
01, and 10. (Code ll.is not used.) Except for special interpreta-
tions, there are four basic patterns for interpreting the codes.
The four patterns (CCA, CCB, CCC, and CCD) are summarized in
table 2-5 and discussed in the following paragraphs.
2-32