HP 3000 III Series Manual page 327

Interrupt System
i. The current instruction (9) is placed in the Index Register.
j. The interrupt condition is cleared (10).
k. The PB-Bank, PB, and PL Registers are set up based on CST en-
try number 1 (11).
1. The Status Register (12) is set to privileged mode, segment 1
with all other bits cleared (%100001).
m. The starting address of the interrupt receiver code is ob-
tained from the STT entry (13) pointed to by the external
program label. The P Register is set to this value and the
CPU fetches the instruction at P and begins executing the
interrupt rece iver code.
Additional ICS-type internal interrupts could occur before exit-
ing from the interrupt code segment and they would be stacked on
the ICS in a manner similar to that shown in figure 8-4. If
there are any external interrupts, either suspended on the ICS or
waiting for priority, they will be processed after all internal
interrupts have been processed. (However, external interrupts can
interrupt internal interrupt routines if the software re-enables
the external interrupt system.) After all internal and external
interrupts using the ICS have been processed, an exit back to the
interrupted user will occur or the Dispatcher may be entered.
8-50. Sequence For Non-ICS Type Interrupts
Figure 8-6 illustrates the processing of
non~ICS
type internal
interrupts. As shown in the figure, the ICS is not used and the
interrupt code segment will operate on the user's stack. Assume
that the user is executing at point P when an interrupt condition
occurs. The CPU passes control to the Interrupt Handler and the
sequence is as follows:
a. Any TOS elements that are in CPU registers (1, figure 8-6)
are pushed into memory.
b. A normal four-word stack marker is pushed onto the user's
stac k (2).
c. The parameter (3)
8-1. )
is pushed onto the stack. (Refer to table
d. The current instruction (4) is placed in the Index Register.
e. The Interrupt Handler generates an external program label (5)
to the interrupt receiver code in segment number 1.
f. The PB-Bank, PB, and PL Registers are set based
on
r
the CST
entry (6).
8-21