HP 3000 III Series Manual page 90

System/CPU Overview
2-104. Program Base Registe r (PB). The Program Base Reg iste r (PB
Register) is a l6-bit register that contains the absolute address
of the bottom location of the current program se9ment. (Refer to
paragraphs 2-21 through 2-28.) The PB Register
1S
read by S-Bus
field code PB and loaded by Store field code PB.
2-105. Data Limit Register (DL). The Data Limit Register (DL
Register) is a l6-bit register that contains the absolute address
of the bottom usable location in the current data stack. (Refer
to paragraphs 2-21 through 2-28.) The DL Register is read by
S-Bus field code DL and loaded by Store field code DL.
2-106. Stack Memory Register (SM). The Stack Memory Register (SM
Register) is a l6-bit register that contains the absolute address
of the top element of the data stack in memory. Depending on the
number of TOS registers in use (specified by contents of
SR Register), this address can be from zero to four locations
be 1 ow the act ua 1 TO S • ( Re fer top a r ag rap hs 2- 21 th r
0
ugh 2 - 28 • )
The SM Register is read by S-Bus field code SM and loaded by
Store field code SM.
2-107. Data Base Register (DB). The Data Base Register (DB
Register is a l6-bit register that is one of the stack limit reg-
isters. The DB Register contains the absolute address of the
first location of directly addressable storage in the current
data stack. (Refer to paragraphs 2-21 through 2-28.) The DB
Register is read by S-Bus field code DB and loaded by Store field
code DB.
2-108.
Q Register (Q). The Q Register is a l6-bit stack
marker
register that contains the absolute address of the current stack
marker being used within the data stack. (Refer to paragraphs
2-21 through 2-28.) The Q
Register is read by S-Bus field code Q
and loaded by Store field code Q.
2-109. Scratch Pad 2 Register (SP2). The Scratch Pad 2 Register
(SP2 Register) is a l6-bit register that is used by the CPU to
store partial results during various microprogram routines. The
SP2 Register is read by S-Bus field code SP2 and loaded by Store
fie ld code SP2.
2-110. Scratch Pad 3 Register (SP3). The Scratch Pad 3 Register
(SP3 Register) is a l6-bit register used by the CPU to store
partial results during various microprogram routines. The
SP3 Register can be right shifted and provides serial data input
to bit 0 and output from bit 15. The SP3 Register is read by
S-Bus field code SP3, loaded by Store field code SP3, and shifted
by Function field codes CTSD, MPAD, and TASR.
2-111. Process Clock Register (PCLOCK). The Process Clock Reg-
ister (PCLOCK Register) is a l6-bit register counter. The
PCLOCK Register is loaded and read by software instructions and
is continuously incremented as long as the CPU is not executing
on the Interrupt Control Stack (ICS FLAG
=
0) or is not halted.
2-58