HP 3000 III Series Manual page 277

I/O System
7-26. I/O Transfer Modes
There are three basic modes of data transfer; direct I/O and two
SIO type transfers. Direct I/O operation consists of the trans-
fer of a single word (per CPU instruction) between the CPU and a
Device Controller. The Multiplexer and Selector Channels are not
involved. Direct I/O operations are discussed in paragraph 7-27.
During the two SIO type transfers, the CPU gives the I/O system a
command to "start I/O" for a particular device and the I/O system
proceeds to execute an I/O progam for that device. The program,
which resides in memory, controls the input and output of data.
Specifically, the two SIO transfer modes are moderate-speed
transfers via the Multiplexer Channel and high-speed transfers
via the Selector Channel. Figure 7-12 illustrates the difference
in data routes for these two modes. However ,the significant dif-
ference is in the sequencing of transfers for multiple Device
Controllers. Paragraphs 7-31 and 7-30 describe the difference
between Multiplexer Channel and Selector Channel transfers.
7-27. DIRECT I/O. During direct I/O operations, the CPU trans-
fers information directly to and fram a Device Controller without
invol ving memory, the Mul tiplexer Channel, or Selector Channel.
(See figure 7-12.) For each I/O instruction, one word is trans-
ferred either to or from the CPU TOS. The CPU has four direct
I/O instr uctions; Test I/O (TIO), Control I/O (CIO), Read I/O
(RIO), and Wr ite I/O (WIO).
Note
Some Device Controllers cannot accept all
direct I/O commands (see the specific sub-
sys tern manual). Howeve r , all Device Con-
trollers will accept a TIO or CIO using
bits 0 and/or 1. Bit 0, the standard con-
trol bi t, causes a mas te r clear of the
subsystem. Bit 1 causes the subsystem in-
terrupt logic to reset.
The TIO instruction obtains the contents of the Device Control-
ler's Status Register and pushes it onto the TOS. When the CPU
encounters a TIO instruction, its TIO microprogram sends a com-
mand word to the lOP Cbntrol circuit (figure 7-10) in the lOP.
The lOP then issues a Service OUt (SO) and a TIO command on the
10CMD lines via the lOP Bus to the device addressed by the Device
Number (OEVNO) code. The addressed device is therefore enabled
to accept and decode the command, and accordingly, reads the con-
tents of the Status Register onto the 100 lines. Sl is also is-
sued which causes the lOP to load the status word into the 10D
Oa ta In Register and informs the CPU that the word is present.
The CPU then issues a Read signal which reads the contents of the
100 Data In Register to the S-Bus. From the S-Bus, the status
word is placed on the U-Bus and pushed onto the stack.
7-23