HP 3000 III Series Manual page 292

I/O System
destination is ready, the ENB is present, the Port Controller has
priority, and the LSEL and HREQ flip-flops are set. LSEL gates
the address from the Selector Channel to the CTL Bus along with
TO, FROM, and MOP. LSEL also pulls the destination's
ROY
line
low. Then, when ENB is present, the HSEL flip-flop is set. HSEL
gates data form the Selector Channel to the CTL Bus along with
TO, FROM, and MOP.
The Read sequence is as follows: A Read on the request lines to
the Port Controller sets the LREQ flip-flop and sets the MOP
flip-flop to the Read state. The TO lines from the Selector
Channel are clocked into the TO Register and the content is com-
pared with the
ROY
line for that module. When the destination is
ready, the ENB is present, the Port Controller has priority, and
the LSEL flip-flop is set. LSEL gates the address from the Se-
lector Channel to the CTL Bus along with TO, FROM, and MOP. LSEL
also sets the Wait flip-fop. Then, when returning data is pre-
sent
on
the bus and the TO and FROM comparisons match, a STRB
signal is sent to the Selector Channel to tell it to accept the
data on the Port Controller Data (PCD) lines.
7-49. INITIATOR SEQUENCE. The following paragraphs describe how
the Selector Channel's program counter is initialized as the
first step in executing an I/O program for one device. The Sel-
ector Channel Bus or iginates at the Selector Channel and is rout-
ed to all Device Controllers controlled by this Selector Channel.
The Selector Channel Bus is similar to the Multiplexer Channel
Bus in purpose, but differs in that it uses 16 lines for transfer
of control, status, and data words between the Device Controller
and Selector Channel: the corresponding Multiplexer Channel Bus
lines are used as service request lines for up to 16 devices.
The in.itiator sequence begins when the CPU encounters an SIO
instr uction. The CPU, under control of its SIO microprogam, out-
puts a' command word to the lOP Control Register. (See figure
7-12.) This initial command is a TIO to see if there is already
an I/O program active on the channel. The lOP issues the TIO
with SO and DEVNO on the lOP Bus. The Device Controller compares
DEVNO with its internal wired device number and a true compari-
son, with SO, causes the Device Controller to return SI to the
lOP with a 16-bit status word on the lOP Bus. (See figure 7-18.)
The CPU microprogram obtains this status word from the lOP and
checks to see that bit 0, the SIO OK bit, is true. This bit will
be true if the device is ready and the Selector Chapnel is inac-
tive. Assuming that the SIO OK bit is true, the CPU microprogram
outputs an SIO command to the lOP Control Register and the lOP
issues the SIO command to the Device Controller. The DEVNO on
the bus is again compared with the internally wired device number
(figure 7-16) and the true result, with SO, enables the I/O Com-
mand (IOCMD) to be decoded. The IOCMD is now SIO which, when
decoded, issues a Request (REQ) signal to the Selector Channel
control logic. The channel then returns Sl to the lOP as an
acknowledgement response. From now on (except for processing an
interrupt), the lOP is not involved. The data gating logic
routes all data transmissions to the DATA lines of the Selector
7-38