HP 3000 III Series Manual page 238

MCU/Main Memory Overview
6-35. NOP. A NOP (No qperation) memory
similar to a read operation. However,
the originating module. The NOP can
phase when there is a system address
write operation, the MOP code sent with
operation (MOP 00) is
no data is transferred to
occur during an address
parity error. During a
the data is a NOP.
6-36. FAULT CORRECTION AND ERROR LOGGING. During a- read opera-
tion, the error handling circuits detect, log, and correct a~l
single-bit data errors. These circuits also
det~ct
double-bit
errors and force bad CTL Bus data parity to alert the receiving
module. Error .checking and correction takes place during the
normal memory cycle. An error logging scheme uniquely reports'
all single-bit errors (or groups of double-bit error pairs) so
that problem chips on the SMA PCA's can be replaced during sched-
uled maintenance. Refer to paragraphs 6-38 through 6-42.
6-31 Memory Servicing Information
Since the fault correction and error logging features of memory
are useful maintenance tools, they are discussed briefly in para-
graphs 6-38 through 6-47 on a how-to-use basis when maintaining,
troubleshooting, or repairing Main Memory. For a more detailed
discussion of these features, refer to the Stand-Alone Memory
Diagnostic D430B, part no. 30000-90004. In addition, the repair
philosophy for each of the memory module PCA's are discussed in
paragraphs 6-48 through 6-50.
Note
Throughout the following fault correction and
error logging discussion, the term "FLI PCA"
pertains to the Fault Logging Interface PCA,
part no. 30009-60002 for the HP 32421A Series
III and to the System Clock/FLI PCA, part no.
30135-60063 for the HP 32435A Series III.
6-38. FAULT CORRECTION. The fault correction logic on the MCL
PCA generates a six-bit check field for each l6-bit memory word
and stores this field along with toe data on the SMA PCA. The
construction of the check field is shown in figure 6-6. It
should be noted that check bits CS, C3, Cl, and CO are generated
to provide even parity for the eight data bits they check and
that check bits C4 and C2 are generated to provide odd parity for
the eight bits they check. Each check bit is generated over a
different eight bits of the data word. The check bits are gener-
ated on each data word for each write operation to memory. The
hardware checks parity over the same data word when the location
is read back from memory. The read from memory includes the
check bits processed on a write operation. If the resulting
check of the data with the check bits is zero, no error has oc-
curred in the write-read sequence. If the resulting check of the
data word with the check bits is non-zero, the parity checker
outputs HOI through H05 which are decoded as shown in figure 6-7
and any single data bit error is corrected by complementing that
bit.
6-14