HP 3000 III Series Manual page 237

MCU/Main Memory Overview
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211
Figure 6-5. SMA PCA Chip Arrangement
b. READ; 350 nsec access, 700 nsec cycle time
c. NO OPERATION (NOP); 700 nsec cycle time
These operations plus fault correction and error logging are dis-
cussed briefly in the following paragraphs.
6-33. READ. A read operation (MOP 10) outputs 17 data bits and
a parity bit from the addressed location to the requesting module
via the CTL Bus. Refer to paragraphs 6-2 through 6-14.
6-34. WRITE. A write operation (MOP 01) loads 17 data bits and
a check bit into a given address location. Two transmissions to
the memory module are required to initiate a write operation.
Refer to paragraphs 6-2 through 6-14.
6-13